View LTM4634-15_8235348.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 typical a pplica t ion fea t ures descrip t ion triple output 5a/5a/4a step-down dc/dc module ? regulator the lt m ? 4634 integrates three complete 5a/5a/4a high efficiency switching mode dc/dc converters into one small package. switching controllers, power fets, inductors, and most support components are included. operating over an input voltage range of 4.75v to 28v, the ltm4634 provides three independent output voltages. v out1 and v out2 are adjustable from 0.8v to 5.5v, while v out3 is adjustable from 0.8v to 13.5v. each output voltage is set by a single external resistor. high switching frequency and a current mode architecture enable a very fast transient response to line and load changes without sacrificing stability. the device supports frequency synchronization, multiphase parallel opera - tion, soft-start and output voltage tracking for supply rail sequencing. fault protection features include over voltage protection, over current protection and temperature monitoring. the power module is offered in a space saving, thermally enhanced 15mm 15mm 5.01mm bga package. the ltm4634 is available with snpb (bga) or rohs compliant terminal finish. 24v input to 3.3v, 5v and 12v output regulator 24v input efficiency a pplica t ions n three independent high efficiency regulator channels n i out1,2 = 5a, i out3 = 4a n input voltage range: 4.75v to 28v n independent v in for each channel n v out1,2 voltage range: 0.8v to 5.5v n v out3 voltage range: 0.8v to 13.5v n 1.5% maximum total dc output error n current mode control/fast transient response n frequency synchronization n output overvoltage and overcurrent protection n polyphase ? operation with current sharing n general purpose temperature monitors n soft-start/voltage t racking n power good monitors n snpb or rohs compliant finish n 15mm 15mm 5.01mm bga package n telecom, networking and industrial equipment n high density point of load voltage regulation l , lt, ltc, ltm, module, polyphase, burst mode, linear technology and the linear logo are registered trademarks and powerpath, ltpowercad and ultrafast are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6580258 and 8163643. other patents pending. 19.1k 3.3v 11.5k 5v 4.32k 12v 10k 40k 2 1f 10k 4.7f 6.3v cntl_pwr run1 run2 run3 tk/ss1 tk/ss2 tk/ss3 pgood12 pgood3 v out1 v fb1 v out2 v fb2 v out3 v fb3 4634 ta01a gnd mode/pllin sgnd v in1 24v in v in2 v in3 ltm4634 intv cc extv cc 5v freq/plllpf load current (a) 0 efficiency (%) 80 85 90 4.54.0 4634 ta01b 75 70 60 1.0 2.0 3.0 0.5 5.0 1.5 2.5 3.5 65 100 95 24v to 3.3v eff (750khz) ch1 24v to 5v eff (750khz) ch2 24v to 12v eff (750khz) ch3 v extvcc = 5v ltm4634 4634f for more information www.linear.com/ltm4634
2 p in c on f igura t ion a bsolu t e maxi m u m r a t ings cntl_pwr ............................................... C 0.3v to 30v v in1 , v in2 , v in3 ........................................... C0 .3v to 30v v out1 , v out2 ........................................... C0 .3v to 5.75v v out3 ......................................................... C0 .3v to 14v switch voltage (sw1, sw2 and sw3) ........... C 1v to 30v mode/pllin, tk/ss1, tk/ss2, tk/ss3, freq/plllpf ....................................... C 0.3v to intv cc comp1, comp2, comp3, v fb1 , v fb2 , v fb3 (note 3) ................................................. C 0.3v to intv cc run1, run2, run3, intv cc , extv cc , pgood12, pgood3 ..................................... C 0.3v to 6v temp1, temp2 ......................................... C 0.3v to 0.8v intv cc peak output current ................................ 100 ma operating junction temperature range (note 2) .................................................. C 40c to 125c storage temperature range .................. C 55c to 125c peak solder reflow body temperature ................. 245 c (note 1) 1 a b c d e f sw3 temp2 g h j k l m gnd tkss2 tk/ss1 tk/ss3 v fb3 v fb2 v fb1 freq/plllpf sgnd v in1 sw1 sw2 v in2 v in3 v out3 top view bga package 144 lead (15mm 15mm 5.01mm) v out2 v out1 gnd gnd comp3 comp2 comp1 pgood12 pgood3 extv cc gnd gnd gnd gnd gnd 2 3 4 5 6 7 8 9 10 11 12 temp1 intv cc cntl_pwr mode/pllin run1 run2 run3 t jmax = 125c, v ja = 7.5c/w, v jcbottom = 4c/w, v jctop = 5c/w v ja derived from 95mm w 76mm pcb with 4-layer, weight = 3.2g v values determined per jesd51-12 o r d er i n f or m a t ion part number pad or ball finish part marking* package type msl rating temperature range (see note 2) device finish code ltm4634ey#pbf sac305 (rohs) ltm4634y e1 bga 4 C40c to 125c ltm4634iy#pbf sac305 (rohs) ltm4634y e1 bga 4 C40c to 125c ltm4634iy snpb (63/37) ltm4634y e0 bga 4 C40c to 125c consult marketing for parts specified with wider operating temperature ranges. *device temperature grade is indicated by a label on the shipping container. pad or ball finish code is per ipc/jedec j-std-609. ? terminal finish part markings: www.linear.com/leadfree ? recommended lga and bga pcb assembly and manufacturing procedures: www.linear.com/umodule/pcbassembly ? lga and bga package and t ray drawings: www .linear.com/packaging ltm4634 4634f for more information www.linear.com/ltm4634
3 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified internal operating temperature range (note 2), otherwise specifications are at t a = 25c. v in = 24v, per the typical application for each regulator channel. symbol parameter conditions min typ max units v in input dc voltage cntl_pwr powered tied to input supply l 4.75 28 v v out(range) output voltage range v out1 , v out2 output voltage range v out3 l l 0.8 0.8 5.5 13.5 v v v out(dc) output voltage, total variation with line and load, v out1 , v out2 , v out3 c in = 22f 3, c out = 100f ceramic 3, r fb = 11.5k, mode/pllin = 0v, v in = 5.5v to 28v, i out1,2 = 0a to 5a, i out3 = 0a to 4a (note 4) l 4.925 5.0 5.075 v input specifications v run run1, run2, run3 pin on threshold v run rising 1.15 1.3 1.4 v v run(hys) run pin hysteresis 175 mv i q(vin) input supply bias current each channel v out = 5v, burst mode operation, i out = 0a v out = 5v, pulse-skipping mode, i out = 0a v out = 5v, switching continuous, i out = 0a shutdown, run = 0v, v in = 24v 0.5 1.6 45 10 ma ma ma a i s(vin) input supply current each channel v in = 12v, extv cc = 5v out v out1,2 = 5v, v out3 = 5v i out1,2 = 5a 2.21 a i out3 = 4a 1.76 a output specifications (note 4) i out(dc) output continuous current range each channel v out1,2 = 5v v out3 = 5v 0 0 5 4 a a ? v out(line) v out line regulation accuracy per channel v out1 = v in from 5.5v to 28v i out = 0a, cntl_pwr tie to v in l 0.015 0.02 %/v ?v out(load) v out load regulation accuracy per channel v out = 5v, i out1,2 = 0a to 5a ch1, ch2, i out3 = 0a to 4a l 0.3 0.5 % v out(ac) output ripple voltage per channel i out = 0a, c out = 100f ceramic 3, v in = 24v, v out = 5v 75 mv ?v out(start) turn-on overshoot per channel c out = 100f ceramic 3, v out = 5v, i out = 0a, tk/ss = 0.01f 50 mv t start turn-on time per channel c out = 100f ceramic 3, v out = 5v, i out = 0a, tk/ss = 0.01f 6 ms v outls peak deviation for dynamic load per channel load: 0% to 50% to 0% of full load, c out = 100f ceramic 3, v out = 5v typical bench data 200 mv t settle settling time for dynamic load step per channel load: 0% to 50% to 0% of full load, c out = 100f ceramic 3, v out = 5v typical bench data 50 s i out(pk) output current limit per channel v out = 5v 8 a control specifications v fb voltage at v fb pin per channel i out = 0a, v out = 5v l 0.794 0.792 0.80 0.80 0.806 0.808 v v i fb current at v fb pin per channel (note 3) C10 C50 na v ovl feedback overvoltage lockout per channel l 0.84 0.86 0.88 v i tk/ss track pin soft-start pull-up current per channel tk/ss = 0v 1.1 1.5 1.9 a t on(min) minimum on-time (note 3) 90 ns max dc maximum duty cycle 5.5v to 5v at 5a (note 5) 95 % r fbhi resistor between v out and v fb pins 60.0 60.4 60.8 k ltm4634 4634f for more information www.linear.com/ltm4634
4 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified internal operating temperature range (note 2), otherwise specifications are at t a = 25c. v in = 24v, per the typical application for each regulator channel. symbol parameter conditions min typ max units v pgood pgood trip level pgood12 pgood3 v fb with respect to set output v fb ramping negative v fb ramping positive C7.5 7.5 % % v pgl pgood voltage low i pgood = 2ma 0.1 0.3 v intv cc linear regulator v intvcc internal v cc voltage float mode/pllin 6v < v in < 28v, i cc = 0ma 4.8 5 5.2 v v ldoint intv cc load regulation i cc = 0ma to 100ma 1 % v extvcc extv cc switchover voltage extv cc ramping positive l 4.5 4.7 v v ldoext extv cc voltage drop i cc = 20ma, v extvcc = 5v 30 75 mv v ldohys extv cc hysteresis 200 mv oscillator and phase-locked loop f sync sync capture range clock input duty cycle = 50% 250 750 khz f s switching frequency v freq/plllpf = intv cc 700 750 825 khz r mode/pllin mode/pllin input resistance 250 k v ih(mode/pllin) clock input level high 2.0 v v il(mode/pllin) clock input level low 0.8 v clock phase v out2 to v out1 phase v out3 to v out2 phase v out1 to v out3 phase v freq/plllpf = 1.2v (note 3) 120 120 120 deg deg deg v temp1,2 temperature diode forward voltage i temp = 100a 0.598 v tc v temp temperature coefficient C2.0 mv/c note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltm4634 is tested under pulsed load conditions such that t j t a . the ltm4634e is guaranteed to meet performance specifications over the 0c to 125c internal operating temperature range. specifications over the C40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltm4634i is guaranteed to meet specifications over the C40c to 125c internal operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 3: 100% tested at wafer level. note 4: see output current derating curves for different v in , v out and t a . note 5: high duty designs need to be validated based on maximum temperature rise and derating in ambient conditions. ltm4634 4634f for more information www.linear.com/ltm4634
5 typical p er f or m ance c harac t eris t ics 24v input efficiency (ch1 and ch2) 12v input efficiency (ch3) 24v input efficiency (ch3) 24v input continuous, pulse- skipping and burst mode operation 5v input efficiency (ch1 and ch2) 5v input efficiency (ch3) 12v input efficiency (ch1 and ch2) load current (a) 0 efficiency (%) 70 80 90 100 4.0 4634 g07 60 50 65 75 85 95 55 45 40 1.0 2.0 3.0 0.5 4.5 1.5 2.5 3.5 5.0 5.0v out (750khz) burst 5.0v out (750khz) pulse 5.0v out (750khz) cont 24v to 5v load step response 24v to 3.3v load step response output 100mv/div load step 1a/div 100s/div 4634 g08 0a to 2.5a, 2.5a/s load step c out = 2 100f ceramic capacitor output 100mv/div load step 1a/div 100s/div 4634 g09 0a to 2.5a, 2.5a/s load step c out = 2 100f ceramic capacitor load current (a) 0 efficiency (%) 70 80 90 100 4.0 4634 g01 60 50 65 75 85 95 55 45 40 1.0 2.0 3.0 0.5 4.5 1.5 2.5 3.5 5.0 5v to 1.0v eff (250khz) 5v to 1.2v eff (250khz) 5v to 1.5v eff (250khz) 5v to 1.8v eff (250khz) 5v to 2.5v eff (250khz) 5v to 3.3v eff (250khz) load current (a) 0 efficiency (%) 70 85 90 4.0 4634 g02 65 60 40 1.0 2.0 3.0 0.5 1.5 2.5 3.5 50 100 95 80 75 55 45 5v to 1.ov eff (250khz) 5v to 1.2v eff (250khz) 5v to 1.5v eff (250khz) 5v to 1.8v eff (250khz) 5v to 2.5v eff (250khz) 5v to 3.3v eff (250khz) load current (a) 0 efficiency (%) 70 80 90 100 4.0 4634 g03 60 50 65 75 85 95 55 45 40 1.0 2.0 3.0 0.5 4.5 1.5 2.5 3.5 5.0 v extvcc = 5v 12v to 1.0v eff (250khz) 12v to 1.2v eff (250khz) 12v to 1.5v eff (250khz) 12v to 1.8v eff (250khz) 12v to 2.5v eff (250khz) 12v to 3.3v eff (250khz) 12v to 5.0v eff (250khz) load current (a) 0 efficiency (%) 70 85 90 4.0 4634 g04 65 60 40 1.0 2.0 3.0 0.5 1.5 2.5 3.5 50 100 95 80 75 55 45 v extvcc = 5v 12v to 1.0v eff (250khz) 12v to 1.2v eff (250khz) 12v to 1.5v eff (250khz) 12v to 1.8v eff (250khz) 12v to 2.5v eff (250khz) 12v to 3.3v eff (250khz) 12v to 5.0v eff (250khz) load current (a) 0 efficiency (%) 70 80 90 100 4.0 4634 g05 60 50 65 75 85 95 55 45 40 1.0 2.0 3.0 0.5 4.5 1.5 2.5 3.5 5.0 v extvcc = 5v 24v to 1.0v eff (250khz) 24v to 1.2v eff (250khz) 24v to 1.5v eff (300khz) 24v to 1.8v eff (350khz) 24v to 2.5v eff (350khz) 24v to 3.3v eff (600khz) 24v to 5.0v eff (750khz) load current (a) 0 efficiency (%) 70 85 90 4.0 4634 g06 65 60 40 1.0 2.0 3.0 0.5 1.5 2.5 3.5 50 100 95 80 75 55 45 v extvcc = 5v 24 to 1.0v eff (250khz) 24 to 1.2v eff (250khz) 24 to 1.5v eff (250khz) 24 to 1.8v eff (300khz) 24 to 2.5v eff (300khz) 24 to 3.3v eff (350khz) 24 to 5.0v eff (500khz) 24 to 12v eff (750khz) ltm4634 4634f for more information www.linear.com/ltm4634
6 typical p er f or m ance c harac t eris t ics 24v to 5v no load short 12v to 1.2v load step response 12v to 1.8v load step response 12v to 2.5v load step response 24v to 5v no load start-up 12v to 1.5v load step response 24v to 12v load step response 12v to 1v load step response 24v to 5v full load start-up output 100mv/div load step 1a/div 100s/div 4634 g10 0a to 2a, 2a/s load step c out = 2 100f ceramic capacitor and 100f 16v 16tqc100myf pos capacitor output 50mv/div load step 1a/div 100s/div 4634 g11 0a to 2.5a, 2.5a/s load step c out = 2 100f ceramic capacitor and 470f 2v 2tpe470majb pos capacitor output 50mv/div load step 1a/div 100s/div 4634 g12 0a to 2.5a, 2.5a/s load step c out = 2 100f ceramic capacitor and 470f 2v 2tpe470majb pos capacitor output 50mv/div load step 1a/div 100s/div 4634 g13 0a to 2.5a, 2.5a/s load step c out = 2 100f ceramic capacitor and 470f 2v 2tpe470majb pos capacitor output 50mv/div load step 1a/div 100s/div 4634 g14 0a to 2.5a, 2.5a/s load step c out = 2 100f ceramic capacitor output 50mv/div load step 1a/div 100s/div 4634 g15 0a to 2.5a, 2.5a/s load step c out = 2 100f ceramic capacitor v out 1v/div i out 1a/div 20ms/div 4634 g16 v in = 24v v out = 5v i out = 0a c out = 2 100f x5r 1210 v out 1v/div i out 1a/div 20ms/div 4634 g17 v in = 24v v out = 5v i out = 5a c out = 2 100f x5r 1210 v out 2v/div i in 1a/div 20s/div 4634 g18 v in = 24v v out = 5v i out = 0a c out = 2 100f x5r 1210 ltm4634 4634f for more information www.linear.com/ltm4634
7 typical p er f or m ance c harac t eris t ics 24v to 5v full load short start-up into pre-bias steady-state output ripple p in func t ions gnd (a4, a8-a9, d1- d12, e1-e12, f4, f8, f12, g3-g4, g7-g8, g11-g12, h3-h4, h7-h8, h11-h12, j1-j5, j7, j9-j12, k1-k3, k8-k10, k12,l1-l2,l12, m1, m6-m8, m12): ground pins for both input and output returns. all ground pins need to connect with large copper areas underneath the unit. v out1 , v out2 , v out3 (a10-a12, b9-b12, and c10-c12); (a5-a7, b5-b8, c6-c8); (a1-a3, b1-b4, c1-c4): power output pins. apply output load between these pins and the gnd pins. recommend placing output decoupling capacitance directly between these pins and the gnd pins. see table 4. temp1 and temp2 (c9, c5): two onboard temperature diodes for monitoring the vbe junction voltage change with temperature. each of these two temperature diode connected pnp transistors is placed in the middle of channel 1 and channel 2, and in the middle of channel?2 and channel 3. see the applications information section and an example in figure 25. leave floating if not used. v in1 ,v in2 ,v in3 (f9-f10,g9-g10,h9-h10);(f5-f6,g5- g6,h5-h6);(f1-f2,g1-g2,h1-h2): power input pins. apply input voltage between these pins and the gnd pins. recommend placing input decoupling capacitance directly between the v in pins and the gnd pins. the v in paths can be all combined from one power source, or powered from independent power sources. see the applications information section. sw1 (f11), sw2 (f7), sw3 (f3): the internal switch node for each of the regulator channels for monitoring the switching waveform. an r-c snubber circuit can be placed on these pins to ground to eliminate switch node ringing noise. cntl_pwr (j6): input supply to an internal bias ldo to power the internal controller and mosfet drivers. the operating voltage range is 4.75v to 28v under all condi - tions. if the voltage at cntl_pwr is 5.8v, the intv cc pin should be tied to cntl_pwr for optimum efficiency. if the voltage at cntl_pwr is >5.8v, leave intv cc float - ing with the recommended decoupling capacitor. to eliminate power loss in the onboard linear regulator and improve efficiency connect a 5v supply at ext v cc . ensure cntl_pwr > extv cc at all times to avoid reverse polarity on the internal bias ldo. v out 2v/div i in 1a/div 20s/div 4634 g19 v in = 24v v out = 5v i out = 5a c out = 2 100f x5r 1210 package row and column labeling may vary among module products. review each package layout carefully. run 5v/div v out1 1v/div sw 10v/div 20ms/div 4634 g20 prebias 1.5v output starting at 0.5v bias 12v input v out ripple 10mv/div sw node 5v/div 2s/div 4634 g21 12v to 3.3v at 5a load ltm4634 4634f for more information www.linear.com/ltm4634
8 p in func t ions intv cc (j8): output of the internal bias ldo for powering internal control circuitry. connect a 4.7f ceramic capaci - tor to ground for decoupling. if the voltage at cntl_pwr is 5.8v , tie the int v cc pin to cntl_pwr for optimum efficiency. if the voltage at cntl_pwr is >5.8v, leave intv cc floating. see the applications information section. sgnd (k6-k7, l6-l7): signal ground connections. the signal ground connection in the module is separated from normal power ground (gnd) by an internal 2.2 resistor. this allows the designer to connect the signal ground pin close to gnd near the external output capacitors on the regulator channels outputs. the entire internal small-signal feedback circuitry is referenced to sgnd, thus allowing for better output regulation. see the recommended layout in the applications information section. extv cc (l3): external bias power input. the internal bias ldo is bypassed whenever the voltage at extv cc is above 4.7v. never exceed 6v at this pin and ensure cntl_pwr > extv cc at all times to avoid reverse polarity on the internal bias ldo. connect a 1f capacitor to ground when used otherwise leave floating. use a 5v bias or 5v output to power this pin to improve efficiency. freq/plllpf (l8): frequency set and pll lowpass filter pin. this pin is driven with a dc voltage to set the oper - ating frequency. the recommended operating frequency will be supplied in the efficiency graphs for optimal per - formance. a specific frequency can be chosen as long as the minimum on-time is not violated, and inductor ripple current is optimized. when an external clock is used, then the freq/plllpf pin must not be connected to any dc voltage. the pin must be floating and will have the proper internal compensation for the internal loop filter. see the applications information section. mode/pllin (l9): forced continuous mode, burst mode, or pulse-skipping mode selection pin and external syn - chronization input to phase detector pin. connect this pin to sgnd to force all channels into the continuous mode of operation. connect to int v cc to enable pulse-skipping mode of operation. leave floating to enable burst mode operation. a clock on the pin will force the controller into continuous mode of operation and synchronize the internal oscillator. see the applications information section. run1, run2, run3 (l10, l11, k11): run control inputs. a voltage above 1.3v on any run pin turns on that par - ticular channel. however, forcing any of these run pins below 1.15v causes that channel to shut down. each of the run pins has an internal 10k resistor to ground. this resistor can be used with an external pull-up resistor to the input voltage to set a uvlo for that channel, or simply to turn on the channel. the run pins have a maximum voltage of 6v. see the applications information section. pgood12, pgood3 (m2, m3): output voltage power good indicator for v out1 and v out2 combined, and v out3 separate. the open-drain logic output is pulled to ground when the output voltage is not within 7.5% of the regula - tion point. comp1, comp2, comp3 (m4, l4, k4): current control threshold and error amplifier compensation point. the current comparator threshold increases with this control voltage. the l tm4634 regulator channels are all internally compensated for proper stability. comp1 and comp2 can be tied together for polyphase 10a parallel operation. see the applications information section. v fb1 , v fb2 , v fb3 (m5, l5, k5): the negative input of the error amplifier for each of the three channels. internally, each of these pins is connected to their respective output with a 60.4k precision resistor. different output voltages can be programmed with an additional resistor between each individual v fb pin and ground. in polyphase operation, tying the v fb1 and v fb2 pins together allows for parallel operation up to 10a. see the applications information section for details. tk/ss1, tk/ss2, tk/ss3 (m9, m10, m11): output voltage tracking and soft-start inputs. when one particular channel is configured to be the master, a capacitor to ground at this pin sets the ramp rate for the master channels output voltage. when the channel is configured to be the slave, the v fb voltage of the master channel is reproduced by a resistor divider and applied to this pin. internal soft-start currents of 1.5a are charging the soft-start capacitors. in dual output (2 + 1) mode, tk/ss1 and tk/ss2 need to be shorted externally. ltm4634 4634f for more information www.linear.com/ltm4634
9 b lock diagra m figure 1. simplified ltm4634 block diagram + mtop1 1.5h 0.1f 1f r fb1 19.1k sgnd sgnd mbot1 mtop2 mbot2 v out1 v fb1 c out1 v fb1 v out1 3.3v 5a v in1 cntl_pwr sw1 gnd gnd temp1 located near power stages internal block diagram c in1 4.7f 50v pnp + 1.5h 0.1f 1f r fbhi2 60.4k r fbhi1 60.4k 2 24v 1f 50v sgnd v out2 v fb2 v in2 c out2 v fb2 v out2 5v 5a sw2 gnd gnd temp2 located near power stages r fb2 11.5k sgnd c in3 4.7f 50v 100f 50v pnp mtop3 mbot3 + 3.3h 0.1f ss cap3 1f r fbhi3 60.4k r run3 10k r5 10k r fb3 4.32k sgnd sgnd sgnd sgnd 2.2 comp3 v out3 tk/ss3 run3 comp2 v fb3 v in3 c out3 v fb3 4634 f01 v out3 12v 4a sw3 gnd gnd r run2 10k run2 pgood3 extv cc intv cc intv cc intv cc r4 10k pgood12 sgnd intv cc 24v r3 150k 24v r2 150k 24v r run1 10k run1 freq/plllpf mode/pllin r1 150k c in5 4.7f 50v 3-channel power control sgnd ss cap2 tk/ss2 sgnd internal comp sgnd internal comp comp1 sgnd 5v internal comp ss cap1 tk/ss1 sgnd sgnd 4.7f internal filter (r1 + 10k)1.3v 10k v in(uvlo) = + ltm4634 4634f for more information www.linear.com/ltm4634
10 o pera t ion power module description the ltm4634 module regulator is a high performance triple output nonisolated switching mode dc/dc power supply. it can provide 5a/5a/4a outputs with a few ex - ternal input and output capacitors. this module provides precisely regulated output voltages programmable via external resistors from 0.8v dc to 5.5v dc (v out1 and v out2 ), and 0.8v dc to 13.5v dc (v out3 ). when apply - ing control bias in the range from 4.75v to 5.8v, then connect the bias to cntl_p wr and int v cc , otherwise if >5.8v only the cntl_pwr pin needs to be biased. the typical application schematic is shown in figure 22. the l tm4634 has three integrated constant-frequency cur - rent mode regulators, power mosfet s, power inductors, and other supporting discrete components. the typical switching frequency is 750khz. for switching noise- sensitive applications, it can be externally synchronized from 250khz to 750khz. operating frequency range will be dependent upon specific v in and v out requirements as they pertain to minimum on-time and inductor ripple current of less than 60% of the load current. see the ap - plications information section. with current mode control and internal feedback loop compensation, the ltm4634 module has sufficient stabil - ity margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. current mode control provides cycle-by-cycle fast current limit in an overcurrent condition. an internal overvoltage monitor protects the output voltages in the event of an overvoltage >10%. the top mosfet is turned off and the bottom mosfet is turned on until the output overvoltage is cleared. there are two temperatures monitors in the ltm4634. temp1 monitors the close relative tempera - ture of channels 1 and 2, and temp2 monitors the close relative temperature of channels 2 and 3. the two diode connected pnp transistors are grounded in the module and can be used as general purpose temperature monitors using a device that is designed to monitor the single-ended connection. pulling any of the run pins below 1.15v forces that regulator channel into a shutdown state. the tk/ss pins are used for programming the output voltage ramp and voltage tracking during start-up for each of the channels. see the applications information section. the ltm4634 is internally compensated to be stable over all operating conditions. table 4 provides a guideline for input and output capacitances for several operating conditions. the ltpowercad? software tool is provided for transient and stability analysis. the v fb pin is used to program the output voltage with a single external resistor to ground. each of the channels, operate 120 phase shift for mul - tiphase operation. v out1 and v out2 can be combined to provide a single 10a output. the two channels will not be operating 180 phase shift, but 120 phase when combined for a 10a design. so the input rms current may be higher than a 180 phase shifted design. see the applications information section for details. high efficiency at light loads can be accomplished with selectable burst mode operation using the mode/pllin pin. these light load features will accommodate battery operation. efficiency graphs are provided for light load op - eration in the typical performance characteristics section. ltm4634 4634f for more information www.linear.com/ltm4634
11 a pplica t ions i n f or m a t ion the typical ltm4634 application circuit is shown in fig - ure?22. external component selection is primarily deter- mined by the maximum load current and output voltage. refer to t able 4 for specific external capacitor requirements for particular applications. v in to v out step-down ratios there are restrictions in the v in to v out step-down ratio that can be achieved for a given input voltage. the v in to v out minimum dropout is a function of load current and at very low input voltage and high duty cycle applications output power may be limited as the internal top power mosfet is not rated for 5a operation at higher ambient temperatures. at very low duty cycles the minimum 100ns on-time must be maintained. see the frequency adjust - ment section and temperature derating curves. output voltage programming the p wm controller has an internal 0.8v 1% reference voltage. as shown in the block diagram, a 60.4k preci - sion internal feedback resistor connects the v out and v fb pins together. the output voltage will default to 0.8v with no feedback resistor. adding a resistor r fb from v fb to ground pro- grams the output voltage: v out = 0.8v ? 60.4k + r fb r fb ? ? ? ? ? ? or r fb = 48.32k v out C 0.8 table 1. v fb resistor table vs various output voltages v out (v) 0.8 1.0 1.2 1.5 1.8 2.5 3.3 5.0 12.0 r fb (k) open 243 121 69.8 48.7 28.7 19.1 11.5 4.32 in the parallel operation the following pins should be tied together, v fb1 and v fb2 pins, comp1 and comp2 pins, tk/ss1 and tk/ss2, and run1 and run2. for parallel operation of v out1 and v out2 , connect v fb1 and v fb2 together with a single resistor to ground whose value is determined by: r fb = 60.4k 2 v out 0.8 C 1 input capacitors the ltm4634 module should be connected to a low ac impedance dc source. additional input capacitors are needed for the rms input ripple current rating. the i cin(rms) equation which follows can be used to calculate the input capacitor requirement for each channel. typically 4.7f to 10f x7r ceramics are a good choice with rms ripple current ratings of ~2a each. a 47f to 100f surface mount aluminum electrolytic capacitor can be used for more input bulk capacitance. this bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. if low impedance power planes are used, then this bulk capacitor is not needed. for a buck converter, the switching duty cycle can be estimated as: d = v out v in without considering the inductor ripple current, for each output, the rms current of the input capacitor can be estimated as: i cin(rms) = i out(max) % ? d ? 1Cd ( ) (1) in the previous equation, % is the estimated efficiency of the power module in decimal form (0.nn) for a given v out -to-v in ratio. the selection of c in is simplified by the 3-phase architec - ture and its impact on the worst-case rms current draw occurs when only one channel is operating. this is true when the three channels are powered from a common v in . the channel with the highest duty cycle d peaking at 0.5 and maximum load current needs to be used in the above formula. this will give the maximum rms capacitor current requirement. increasing the output current drawn from the other channels will actually decrease the input rms ripple current from its maximum value. the out-of- phase technique typically reduces the input capacitors rms ripple current by a factor of 50% when compared to a single phase power supply solution. if the three channels are powered from independent input sources, then each ltm4634 4634f for more information www.linear.com/ltm4634
12 a pplica t ions i n f or m a t ion of the input rms current ratings will need to be calculated specific to that channel. output capacitors the ltm4634 is designed for low output voltage ripple noise. the bulk output capacitors defined as c out are chosen with low enough effective series resistance (esr) to meet the output voltage ripple and transient require - ments. c out can be a low esr tantalum capacitor, low esr polymer capacitor or ceramic capacitor. the typical output capacitance range is from 200f to 470f. additional output filtering may be required by the system designer if further reduction of output ripple or dynamic transient spikes is required. table 4 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 5a/s transient. the table optimizes total equivalent esr and total bulk capacitance to optimize the transient performance. stability criteria are considered in the table 4 matrix, and ltpowercad is available for stability analysis. ltpowercad can calculate the output ripple reduction as the number of implemented phases increases by n times. burst mode operation the ltm4634 is capable of burst mode operation in which the power mosfets operate intermittently based on load demand, thus saving quiescent current. for ap - plications where maximizing the efficiency at very light loads is a high priority, burst mode operation should be applied. t o enable burst mode operation, simply float the mode/pllin pin. during burst mode operation, the peak current of the inductor is set to approximately 30% of the maximum peak current value in normal operation even though the voltage at the comp pin indicates a lower value. the voltage at the comp pin drops when the inductors average current is greater than the load requirement. as the comp voltage drops below 0.5v, the burst comparator trips, causing the internal sleep line to go high and turn off both power mosfets. in sleep mode, the internal circuitry is partially turned off, reducing the quiescent current. the load current is now being supplied from the output capacitors. when the output voltage drops, causing comp to rise, the internal sleep line goes low, and the ltm4634 resumes normal operation. the next oscillator cycle will turn on the top power mosfet and the switching cycle repeats. pulse-skipping mode operation i n applications where low output ripple and high efficiency at intermediate currents are desired, pulse-skipping mode should be used. pulse-skipping operation allows the ltm4634 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. tying the mode/pllinpin to intv cc enables pulse-skipping operation. with pulse-skipping mode at light load, the internal current comparator may remain tripped for several cycles, thus skipping operation cycles. this mode has lower ripple than burst mode operation and maintains a higher frequency operation than burst mode operation. forced continuous operation in applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. forced continuous operation can be enabled by tying the mode/pllin pin to ground. in this mode, inductor current is allowed to reverse during low output loads, the comp voltage is in control of the current comparator threshold throughout, and the top mosfet always turns on with each oscillator pulse. during start-up, forced continuous mode is disabled and inductor current is prevented from reversing until the ltm4634 output voltage is in regulation. frequency synchronization the ltm4634 device operates up to 750khz. it can also be synchronized with an input clock that has a high level above 2v and a low level below 0.8v at the mode/pllin pin. the freq/plllpf pin must be floating when synchronized to an incoming clock. once the ltm4634 is synchronized to an external clock frequency, it will always be running in forced continuous operation. the synchronizing range is from 250khz to 750khz. for v out1,2,3 1.5v use 250khz to 300khz, 1.5v v out1,2,3 2.5v use 400khz, 2.5v v out1,2,3 5v use 600khz. if v out3 is greater than 5v up to 12v set the operating frequency to 750khz. these ltm4634 4634f for more information www.linear.com/ltm4634
13 a pplica t ions i n f or m a t ion frequencies optimize efficiency, eliminate minimum on- time issues for less than 1v output, and control the inductor ripple currents over the input and output voltage ranges. 24v input applications that convert to output voltages equal to 5v (v out1,2 ) and up to 12v (v out3 ) will be required to set the ltm4634 switching frequency to 750khz. this is required to maintain less than 60% inductor ripple current at the higher output voltages. the 750khz requirement for these higher output conversions from 24v will limit output voltages on other channels to be no lower than 1.5v due to minimum on-time considerations. there is a way around this issue by taking one of these outputs, either 5v or 12v, and using it as the source for the 0.8v to 1.5v output. an example circuit is shown in figure 26. 5v and 12v input conversions on all three channels can be oper - ated at lower frequencies across the output ranges so that minimum on-time is not an issue at low output voltages. the minimum on-time equation on the next page can be used to verify that no switching frequency is violating this parameter. the equations for checking i ripple %: v in C v out ( ) v out l ? i ripple ? v in = freq, i ripple ch#maxload = i ripple % this verifies that the operating frequencies are selected to limit inductor ripple currents to be below 60% of maximum load, where freq is selected frequency in hertz, i ripple and maximum load current in amps, and l is inductance in henrys. ch1, ch2 l = 1.5h, and ch3 l = 3.3h. maxi - mum load current i out1,2 = 5a, and i out3 = 4a, therefore i ripple should try to stay below 2.5a for ch1, ch2, and 2a for ch3, except for 12v output. the efficiency curves will show the recommended optimal operating frequency for the different conversions a dc voltage should be applied to the freq/plllpf pin to set the operating frequency when clock synchroniza - tion is not used. figure 2 shows the frequency selection as a function of the applied dc voltage. this can be done with a voltage divider from the intv cc (5v) pin to sgnd. a 10k resistor can be selected as the bottom resistor. the top resistor, r freq , can be determined by using equation: r freq = 5v ? 10k freqv C 10k where freqv is the voltage at the freq/plllpf pin in figure 2 that corresponds to a particular frequency. see figure 25 for an example. freq/plllpf pin voltage (v) 0 frequency (khz) 0.5 1 1.5 2 4634 f02 2.5 300 400 500 800 700 200 600 figure 2. relationship between oscillator frequency and voltage at the freq/plllpf pin parallel channel operation for outputs that demand more than 5a of load current, the ltm4634 device can parallel v out1 and v out2 to sup - ply 10a of load current. the two channels will operate at 120 of phase shift. the input rms ripple current can be calculated using equation 1. for example, 12v to 1.2v at 10a equates to duty cycle d = 0.1. i cin(rms) = 10a 0.85 ? 0.1 ? 1C 0.1 ( ) i cin(rms) = 3.5a rms , use 2 22f 16v x5r or x7r ceramic capacitors rated at 2a rms each. the ltm4634 regulators are inherently current mode controlled devices, so the paralleling of v out1 and v out2 channels will have good current sharing. this will balance the thermals in the design. tie the comp, v fb , tk/ss and run pins together for these two channels to share the current evenly. figure 24 shows a schematic of the parallel design. minimum on-time minimum on-time, t on , is the smallest time duration that any of the three regulator channels is capable of turning on the top mosfet. it is determined by internal timing delays, and the gate charge required to turn on the top mosfet. ltm4634 4634f for more information www.linear.com/ltm4634
14 a pplica t ions i n f or m a t ion low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: v out v in ? freq > t on(min) if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the output ripple and inductor ripple current will increase. the minimum on-time can be increased by lowering the switching frequency. a good rule of thumb is to use a 100ns on-time. output voltage tracking output voltage tracking can be programmed externally using the tk/ss pins. the output can be tracked up and down with another regulator. the master regulators output is divided down with an external resistor divider that is the same as the slave regulators feedback divider to imple - ment coincident tracking. the ltm4634 uses an accurate 60.4k resistor internally for the top feedback resistor for each channel. figure 3 shows an example of coincident tracking for v out1 and v out2 . v out1 is the master and v out2 is the slave: v slave = 1 + 60.4k r ta ? ? ? ? ? ? v track v track is the track ramp applied to the slaves track pin. v track has a control range of 0v to 0.8v, or the internal reference voltage. when the masters output is divided down with the same resistor values used to set the slaves output, then the slave will coincident track with the master until it reaches its final value. the master will continue to its final value from the slaves regulation point. voltage tracking is disabled when v track is more than 0.8v. r ta in figure 3 will be equal to the r fb2 for coincident tracking. the tk/ss pin of the master can be controlled by a capaci - tor placed on the master regulator tk/ss pin to ground. a 1.5a current source will charge the tk/ss pin up to the r fb3 19.1k r fb2 121k r fb1 69.8k c out8 100f c out2 220f 47pf 1.5v v fb1 v fb1 v fb2 1.2v 3.3v c out5 220f 220pf v fb3 47pf c out1 220f c ss3 0.1f v out3 v out3 r ta 121k soft-start master ramp set by c ss3 or external ramp uvlo set at 4.7v on run pins. run pins can be sequenced or enabled from logic control c out , see table 5 r tb 60.4k 60.4k 69.8k 7.87k c in1 22f 16v c in2 22f 16v c in3 22f 16v c in4 22f 16v c out4 220f c out7 100f 10k 10k cntl_pwr mode/pllin run1 run2 run3 tk/ss2 tk/ss3 freq/plllpf comp1 comp2 comp3 pgood12 pgood3 temp1 temp2 v out1 v fb1 v out2 v fb2 v out3 v fb3 4633 f03 gnd sgnd v in1 sw1 v in2 5.5v to 16v sw2 v in3 ltm4634 sw3 4.7f 6.3v intv cc extv cc tk/ss1 v fb2 v fb3 master figure 3. triple outputs (1.5v and 1.2v) with tracking and 3.3v ltm4634 4634f for more information www.linear.com/ltm4634
15 a pplica t ions i n f or m a t ion reference voltage and then proceed up to intv cc . after the 0.8v ramp, the tk/ss pin will no longer be in control, and the internal voltage reference will control output regula - tion from the feedback divider. foldback current limit is disabled during this sequence of turn-on during tracking or soft-starting. the tk/ss pins are pulled low when the run pin is below 1.15v or intv cc drops below 3.5v. the total soft-start time can be calculated as: t ss = 0.8v ? c ss 1.5a ? ? ? ? ? ? regardless of the mode selected by the mode/pllin pin, the regulator channels will always start in pulse-skipping mode up to tk/ss = 0.64v. between tk/ss = 0.64v and 0.74v, it will operate in forced continuous mode and revert to the selected mode once tk/ss > 0.74v. the output ripple is minimized during the 100mv forced continuous mode window ensuring a clean pgood signal. when the channel is configured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the tk/ss pin. therefore, the voltage ramp rate on this pin is determined by the ramp rate of the other supplys voltage. note that the small soft- start capacitor charging current is always flowing, produc - ing a small offset error. to minimize this error, select the tracking resistive divider value to be small enough to make this error negligible. in order to track down another channel or supply after the soft-start phase expires, the l tm4634 is forced into continuous mode of operation as soon as v fb is below the undervoltage threshold of 0.74v regardless of the setting of the mode/pllin pin. however, the ltm4634 should always be set in forced continuous mode tracking down when there is no load. after tk/ss drops below 0.1v, its channel will operate in discontinuous mode. the masters tk/ss pin slew rate is directly equal to the masters output slew rate in volts/time. the equation: r tb = mr sr ? ? ? ? ? ? ? 60.4k where mr is the masters output slew rate and sr is the slaves output slew rate in volts/time. when coincident tracking is desired, then mr and sr are equal, thus r tb is equal the 60.4k. r ta is derived from equation: r ta = 0.8v v fb 60.4k + v fb r fb C v track r tb where v fb is the feedback voltage reference of the regula - tor, and v track is 0.8v. since r tb is equal to the 60.4k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then r ta is equal to r fb with v fb = v track . therefore r tb = 60.4k, and r ta = 60.4k in figure 3. in ratiometric tracking, a different slew rate maybe desired for the slave regulator. r tb can be solved for when sr is slower than mr. make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach it final value before the master output. power good the pgood12 pin is an open-drain pin that can be used to monitor valid output voltage regulation for v out1 and v out2 , and pgood3 for monitoring v out3 . these pins monitor a 7.5% window around the 0.8v feedback volt- age on either v fb1,2,3 from the output regulation point. a resistor can be pulled up to a particular supply voltage no greater than 6v maximum for monitoring. any of the pgood pins are pulled low when the run pin of the cor - responding channel is pulled low. overcurrent and over voltage protection each of the regulator channels senses the peak inductor current on a cycle-by-cycle basis in current mode opera - tion. when current limit is reached the output voltage will begin to fall and the internal current limit threshold will begin fold back as the output voltage falls below 50% of its value. foldback current limit is disabled during start- up or track-up. under short-circuit condition at low duty cycle operation, each of the regulator channels will begin to skip cycles to limit the short-circuit current. overvoltage protection is implemented by monitoring each one of the regulators v fb pins. when the v fb volt- age exceeds ~7.5% of the 0.8v reference value, then an ltm4634 4634f for more information www.linear.com/ltm4634
16 a pplica t ions i n f or m a t ion internal comparator monitor will turn off the top power switch, and turn on the bottom power switch to protect the load. if the top power switch faults as a short, then a fuse or circuit breaker would be recommended to protect the system. this is due to the top switch being shorted while the bottom switch is turning on to protect the output from over voltage. high currents will flow and could damage the bottom switch. stability compensation the module has already been internally compensated for all output voltages. table 4 is provided for most applica - tion requirements with verified stability. ltpowercad is available for other control loop optimization. run enable the run 1, 2, 3 pins have an enable threshold of 1.4v maximum, typically 1.3v with 175mv of hysteresis. they control the turn-on of their respective channel. there is a 10k resistor on each pin to ground. the run pins can be pulled up to v in for 5v operation, or a resistor can be placed on the pins and connected to v in for higher than 5v input. this resistor can be set along with the onboard 10k resistor such that an undervoltage lockout (uvlo) level can be programmed to shut down a particular regulator channel if v in falls below a set value. use the equation: r = 10k uvlo C 1.3v ( ) 1.3v where r is the resistor from the run pin to v in to set the uvlo trip point. for example, if the uvlo point is to be 6.25v while operating at 12v input: r = 10k 6.25v C 1.3v ( ) 1.3v 38k see the block diagram in figure 1. the run pins must never exceed 6v maximum voltage. the run pins have to be pulled up to enable the regulators. sw pins the sw pins are generally for testing purposes by moni - toring the pin. the sw pin can also be used to dampen out switch node ringing caused by lc parasitics in the switched current path. usually a series r-c combination is used called a snubber cir cuit. the resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing across the resistor . if the stray inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. the inductance is usually easier to predict. it combines the powerpath? board inductance in combination with the mosfet inter- connect inductance. first the sw pin can be monitored with a wide bandwidth scope with a high frequency scope probe. the ring fre - quency can be measured for its value. the impedance, z, can be calculated: z (l) = 2 ? f ? l where f is the resonant frequency of the ring, and l is the total parasitic inductance in the switch path. if a resistor is selected that is equal to z, then the ringing should be dampened. the snubber capacitor value is chosen so that its impedance is equal to the resistor at the ring frequency. calculated by: z (c) = 1 2 ? f ? c these values are a good place to start with. modification to these components should be made to attenuate the ring - ing without lowering the regulators conversion efficiency. int v cc and extv cc the ltm4634 has an onboard linear regulator fed by cntl_pwr which delivers a roughly 5v output at intv cc to power the internal controller and mosfet drivers for all three regulator channels. apply a 4.7f ceramic capacitor between intv cc and ground for decoupling. cntl_pwr requires a voltage between 4.75v to 28v. if the voltage supplied to cntl_pwr is 5.8v, connect intv cc to cntl_pwr. otherwise, intv cc should be left floating. to eliminate power loss in the onboard linear regulator and improve efficiency connect a supply from 4.7v to 6v at extv cc . biasing extv cc at 5v will reduce the power loss in the internal ldo by (v cntl_pwr C 5v) ? 90ma and is recommended for v cntrl_power 12v when all three channels are operating. if extv cc is used add a 1f ltm4634 4634f for more information www.linear.com/ltm4634
17 a pplica t ions i n f or m a t ion ceramic capacitor to ground at extv cc and ensure the voltage at cntl_pwr is always greater than the voltage at extv cc at all times during start-up and shutdown. connecting v out3 to extv cc may present a convenient way to meet the sequencing requirement. otherwise float extv cc if not used. thermal considerations and output current derating the thermal resistances reported in the pin configuration section of the data sheet are consistent with those param - eters defined by jesd51-12 and are intended for use with finite element analysis (fea) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation per formed on a module package mounted to a hardware test board. the motivation for providing these thermal coefficients is found in jesd51-12 (guidelines for reporting and using electronic package thermal information). many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the module regulators thermal performance in their appli - cation at various electrical and environmental operating conditions to compliment any fea activities. without fea software, the thermal resistances reported in the pin con - figuration section are, in and of themselves, not relevant to providing guidance of thermal per formance; instead, the derating curves provided in the data sheet can be used in a manner that yields insight and guidance pertaining to ones application usage, and can be adapted to correlate thermal performance to ones own application. the pin configuration section gives four thermal coeffi- cients explicitly defined in jesd51-12. these coefficients are quoted or paraphrased as follows: 1. ja : the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclo - sure. this environment is sometimes referred to as still air although natural convection causes the air to move. this value is determined with the part mounted to a 95mm 76mm pcb with four layers. 2. jcbottom : the thermal resistance from the junction to the bottom of the product case, is determined with all of the internal power dissipation flowing through the bottom of the package. in a typical module regulator, the bulk of the heat flows out the bottom of the pack - age, but there is always heat flow out into the ambient environment. as a result, this thermal resistance value may be useful for comparing packages but the test conditions dont generally match the users application. 3. jctop : the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. as the electrical connections of the typical module regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. as in the case of jcbottom , this value may be useful for comparing packages but the test conditions dont generally match the users application. 4. jb : the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the module package and into the board, and is really the sum of the jcbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. the board temperature is measured at a specified distance from the package. a graphical representation of the aforementioned ther - mal resistances is given in figure 4; blue resistances are contained within the module regulator , whereas green resistances are external to the module package. as a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by jesd51-12 or provided in the pin configuration section replicates or conveys normal oper - ating conditions of a module regulator. for example, in normal board-mounted applications, never does 100% of the devices total power loss (heat) thermally con - duct exclusively through the top or exclusively through ltm4634 4634f for more information www.linear.com/ltm4634
18 a pplica t ions i n f or m a t ion bottom of the module packageas the standard defines for jctop and jcbottom , respectively. in practice, power loss is thermally dissipated in both directions away from the packagegranted, in the absence of a heat sink and airflow; a majority of the heat flow is into the board. within the ltm4634, be aware there are multiple power devices and components dissipating power, with a con- sequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. to reconcile this complication without sacrificing modeling simplicity but also, not ignoring practical realitiesan approach has been taken using fea software modeling along with laboratory testing in a controlled environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) initially, fea software is used to accurately build the mechanical geometry of the ltm4634 and the specified pcb with all of the cor - rect material coefficients along with accurate power loss sour ce definitions; (2) this model simulates a software- defined jedec environment consistent with jesd51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the jedec-defined thermal resistance values; (3) the model and fea software is used to evaluate the ltm4634 with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with ther - mocouples within a controlled environment chamber while operating the device at the same power loss as that which was simulated. the outcome of this process and due diligence yields the set of derating cur ves shown in this data sheet. after these laborator y tests have been performed and cor - related to the ltm4634 model, then the jb and ba are summed together to correlate quite well with the device model conditions of no airflow or heat sinking in a properly define chamber. this jb + ba value should accurately equal the ja value because approximately 100% of power loss flows from the junction through the board into ambi - ent with no air-flow or top mounted heat sink. l tm4634 thermal considerations and output current derating the power loss cur ves at 5v input, 12v input, and 24v input are shown in figures 8 to 13. these power loss curves can be used in coordination with the load current derating curves in figures 14 to 21 for calculating an approximate ja thermal resistance for the ltm4634 with various heat sinking and airflow conditions. the power loss curves are taken at room temperature, and are increased with a multiplicative factor of 1.4 at 120c junction. 4633 f04 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient resistance components case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction ambient case (bottom)-to-board resistance figure 4. graphical representations of jesd51-12 thermal coefficients ltm4634 4634f for more information www.linear.com/ltm4634
19 a pplica t ions i n f or m a t ion the derating curves are plotted with the output current starting at 15a (5a/ch) and the ambient temperature at ~40c. the 15a comes from each of the three channels operating at 5a each. this simplifies the loading for this thermal testing. the output voltages are 3.3v, and 5v when all three channels are loaded together in parallel. channel? 1 and channel 2 are designed to operate with outputs up to 5v, and channel 3 is designed for 12v. the power loss curve values at a particular output voltage and output current for each output are taken and multiplied by 1.4 for increased power loss at 120c junction. thermal models are derived from several temperature measure - ments in a controlled temperature chamber along with thermal modeling analysis. the junction temperatures are monitored while ambient temperature is increased with and without airflow. the power loss increase with ambient temperature change is factored into the derating curves. the junctions are maintained at 120c maximum while lowering output current or power with increasing ambient temperature. the decreased output current will decrease the internal module loss as ambient tempera - ture is increased. the monitored junction temperature of 120c minus the ambient operating temperature specifies how much module temperature rise can be allowed. as an example, in figure 17 the 5.0v load current is derated to ~12.6a at ~71c with no air and with no heat sink. in figure 10, the 12v to 5.0v power loss at 4.2a per chan - nel is 1.25w. the total loss would be 3 times 1.25w for 3.75w total power loss. the 3.75w is then multiplied by the 1.4 multiplier for 120c junction. this 5.25w value is used with the total temperature rise of 120c minus the 71c ambient to calculate ja thermal resistance. if the 71c ambient temperature is subtracted from the 120c junction temperature, then the difference of 49c divided 5.25w equals a 9.3c/w ja thermal resistance. table?2 specifies a 9.0c/w value which is very close. tables 2 and?3 provide equivalent thermal resistances for 3.3v and 5v outputs with and without air flow and heat sinking. the derived thermal resistances in tables?2 and 3 for the various conditions can be multiplied by the calculated power loss as a function of the 120c maximum junction tempera - ture to determine if the temperature rise plus ambient is below the 120c maximum junction temperature. thermal measurements or infrared analysis should be per formed to validate the values. ambient temperature power loss can be derived from the power loss cur ves in figures 8 to 13 and adjusted with the 1.4 multiplier. the printed circuit board is a 1.6mm thick four-layer board with two ounce copper for the two outer layers and 1 ounce copper for the two inner layers. the pcb dimensions are 95mm 76mm. the bga heat sinks are listed in table 3. temperature monitoring (temp1 and temp2) diode connected pnp transistors are used for the temp1, temp2 monitoring function since the diode forward voltage varies with temperature. the temperature dependence of the diodes can be understood in the equation: v d = nv t ln i d i s ? ? ? ? ? ? where v t is the thermal voltage (kt/q), and n, the ideality factor, is 1 for the two diode connected pnps being used in the ltm4634. i s is expressed by the typical empirical equation: i s = i 0 exp Cv g0 v t ? ? ? ? ? ? where i 0 is a process and geometry-dependent current (i 0 is typically around 20 orders of magnitude larger than i s at room temperature), and v g0 is the band gap voltage of 1.2v extrapolated to absolute zero or C273c. if we take the i s equation and substitute into the v d equa- tion, then we get: v d = v g0 C kt q ? ? ? ? ? ? ln i 0 i d ? ? ? ? ? ? , v t = kt q the expression shows that the diode voltage decreases (linearly if i 0 were constant) with increasing temperature and constant diode current. figure 5 shows a plot of v d vs temperature over the operating temperature range of the ltm4634. ltm4634 4634f for more information www.linear.com/ltm4634
20 a pplica t ions i n f or m a t ion if we take this equation and differentiate it with respect to temperature t, then: dv d dt = C v g0 C v d t this dv d /dt term is the temperature coefficient equal to about C2mv/k or C2mv/c. the equation is simplified for the first order derivation. solving for t, t = C(v g0 C v d )/(dv d /dt) provides the temperature. 1st example: figure 5 for 27c, or 300k the diode voltage is 0.598v, thus, 300k = C(1200mv C 598mv)/ C2.0 mv/k) 2nd example: figure 5 for 75c, or 350k the diode voltage is 0.50v, thus, 350k = C(1200mv C 500mv)/ C2.0mv/k) converting the kelvin scale to celsius is simply taking the kelvin temp and subtracting 273 from it. a typical forward voltage is given in the electrical charac - teristics section of the data sheet, and figure 5 is the plot of this for ward voltage. measure this for ward voltage at 27c to establish a reference point. then using the above expression while measuring the forward voltage over temperature will provide a general temperature monitor. connect resistors between temp1, temp2 and v in to set the currents to 100a each. see figure 25 for an example. safety considerations the ltm4634 module does not provide galvanic isolation from v in to any of the three v out s. there is no internal fuse. if required, a slow blow fuse with a rating higher than the maximum input current can be used to protect the unit in case of a catastrophic failure. an inline circuit breaker function can also be used instead of a fuse. the fuse or circuit breaker should be selected to limit the current to the regulator during overvoltage in case of an internal top mosfet fault. if the internal top mosfet fails, then turning it off will not resolve the overvoltage, thus the internal bottom mosfet will turn on indefinitely trying to protect the load. under this fault condition, the input voltage will source very large currents to ground through the failed internal top mosfet and enabled internal bot - tom mosfet. this can cause excessive heat and board damage depending on how much power the input voltage can deliver to this system. a fuse or cir cuit breaker can be used as a secondar y fault protector in this situation. figure 5. diode voltage v d vs temperature t(c) figure 6. thermal plot 24v to 3.3v at 5a, 5v at 5a, and 12v at 4a, airflow = 200lfm, ambient = 25c temperature (c) ?50 ?25 0.3 diode voltage (v) 0.5 0.8 0 50 75 0.4 0.7 0.6 25 100 4634 f05 125 i d = 100a ltm4634 4634f for more information www.linear.com/ltm4634
21 a pplica t ions i n f or m a t ion layout checklist/example the high integration of ltm4634 makes the pcb board layout very simple and easy. however, to optimize its electri - cal and thermal performance, some layout considerations are still necessary . use large pcb copper areas for high current paths, in - cluding v in , gnd, v out1 , v out2 , and v out3 . it helps to minimize the pcb conduction loss and thermal stress. place high frequency ceramic input and output capacitors next to the v in , gnd and the v out pins to minimize high frequency noise. place a dedicated power ground layer underneath the unit. to minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection be - tween top layer and other power layers. do not put vias directly on the pads, unless they are capped or plated over. use a separated sgnd ground copper area for components connected to signal pins. connect the sgnd to gnd underneath the unit. bring out test points on the signal pins for monitoring. figure 7 gives a good example of the recommended layout. gnd m l k j h g f e d c b a 2 3 4 5 6 7 8 9 10 11 12 4634 f07 c out1 c out4 c out2 c out5 c out3 c out6 ?a1? indicator c in3 gnd gnd gnd v out1 v out3 gnd v in3 v out3 gnd gnd v out2 ltm4634y bga top view v out1 c in1 farside components c in1 , c in2 1 control c intvcc control r fb1 r fb2 r fb3 farside components c out4 , c out5, c out6 farside components r fb1 , r fb2 , r fb3 c in2 figure 7. recommended pcb layout ltm4634 4634f for more information www.linear.com/ltm4634
22 figure 11. 12v power loss (ch3) figure 12. 24v power loss (ch1 and ch2) figure 13. 24v power loss (ch3) figure 8. 5v input power loss (ch1 and ch2) figure 9. 5v input power loss (ch3) figure 10. 12v input power loss (ch1 and ch2) a pplica t ions i n f or m a t ion load current (a) 0 0 power loss (w) 0.2 0.4 0.6 1.4 1.0 1.0 2.0 2.5 4.5 1.2 0.8 0.1 0.3 0.5 1.3 0.9 1.1 0.7 0.5 1.5 3.0 3.5 4.0 5.0 4634 f08 5v to 3.3v power loss curve 5v to 2.5v power loss curve 5v to 1.8v power loss curve 5v to 1.5v power loss curve 5v to 1.2v power loss curve 5v to 1v power loss curve load current (a) 0 0 power loss (w) 0.2 0.4 0.6 1.4 1.0 1.0 2.0 2.5 4.5 1.2 0.8 0.1 0.3 0.5 1.3 0.9 1.1 0.7 0.5 1.5 3.0 3.5 4.0 5.0 4634 f09 5v to 3.3v power loss curve 5v to 2.5v power loss curve 5v to 1.8v power loss curve 5v to 1.5v power loss curve 5v to 1.2v power loss curve 5v to 1v power loss curve load current (a) 0 0 power loss (w) 0.2 0.4 0.6 1.6 1.0 1.0 2.0 2.5 4.5 1.2 0.8 0.1 0.3 0.5 1.3 1.4 1.5 0.9 1.1 0.7 0.5 1.5 3.0 3.5 4.0 5.0 4634 f10 12v to 5v power loss curve 12v to 3.3v power loss curve 12v to 2.5v power loss curve 12v to 1.8v power loss curve 12v to 1.5v power loss curve 12v to 1.2v power loss curve 12v to 1v power loss curve load current (a) 0 0 power loss (w) 0.2 0.4 0.6 1.8 1.0 1.0 2.0 2.5 4.5 1.2 0.8 0.1 0.3 0.5 1.3 1.4 1.5 1.6 1.7 0.9 1.1 0.7 0.5 1.5 3.0 3.5 4.0 5.0 4634 f11 12v to 5v power loss curve 12v to 3.3v power loss curve 12v to 2.5v power loss curve 12v to 1.8v power loss curve 12v to 1.5v power loss curve 12v to 1.2v power loss curve 12v to 1v power loss curve load current (a) 0 0 power loss (w) 0.2 0.4 0.6 1.8 2.0 2.2 2.4 1.0 1.0 2.0 2.5 4.5 1.2 0.8 1.4 1.6 0.5 1.5 3.0 3.5 4.0 5.0 4634 f12 24v to 5v power loss curve 24v to 3.3v power loss curve 24v to 2.5v power loss curve 24v to 1.8v power loss curve 24v to 1.5v power loss curve 24v to 1.2v power loss curve 24v to 1v power loss curve load current (a) 0 0 power loss (w) 0.2 0.4 0.6 1.8 2.0 2.2 2.4 1.0 1.0 2.0 2.5 4.5 1.2 0.8 1.4 1.6 0.5 1.5 3.0 3.5 4.0 5.0 4634 f12 24v to 12v power loss curve 24v to 5v power loss curve 24v to 3.3v power loss curve 24v to 2.5v power loss curve 24v to 1.8v power loss curve 24v to 1.5v power loss curve 24v to 1.2v power loss curve 24v to 1v power loss curve ltm4634 4634f for more information www.linear.com/ltm4634
23 a pplica t ions i n f or m a t ion figure 14. 12v in , 3.3v out , with heat sink, all channels at 5a each figure 17. 12v in , 5v, without heat sink, all channels at 5a each figure 15. 12v in , 3.3v out , without heat sink, all channels at 5a each figure 18. 24v in , 3.3v, with heat sink, all channels at 5a each figure 20. 24v in , 5v, with heat sink, all channels at 5a each figure 16. 12v in , 5v, with heat sink, all channels at 5a each figure 19. 24v in , 3.3v, without heat sink, all channels at 5a each figure 21. 24v in , 5v, without heat sink, all channels at 5a each temperature (c) 0 total output current (a) 8 4634 f14 4 0 40 80 20 60 100 12 16 6 2 10 14 120 0 lfm air flow 200 lfm air flow 400 lfm air flow temperature (c) 0 total output current (a) 8 4634 f15 4 0 40 80 20 60 100 12 16 6 2 10 14 120 0 lfm air flow 200 lfm air flow 400 lfm air flow temperature (c) 0 total output current (a) 8 4634 f16 4 0 40 80 20 60 100 12 16 6 2 10 14 120 0 lfm air flow 200 lfm air flow 400 lfm air flow temperature (c) 0 total output current (a) 8 4634 f17 4 0 40 80 20 60 100 12 16 6 2 10 14 120 0 lfm air flow 200 lfm air flow 400 lfm air flow temperature (c) 0 total output current (a) 8 4634 f18 4 0 40 80 20 60 100 12 16 6 2 10 14 120 0 lfm air flow 200 lfm air flow 400 lfm air flow temperature (c) 0 total output current (a) 8 4634 f19 4 0 40 80 20 60 100 12 16 6 2 10 14 120 0 lfm air flow 200 lfm air flow 400 lfm air flow temperature (c) 0 total output current (a) 8 4634 f20 4 0 40 80 20 60 100 12 16 6 2 10 14 120 0 lfm air flow 200 lfm air flow 400 lfm air flow temperature (c) 0 total output current (a) 8 4634 f21 4 0 40 80 20 60 100 12 16 6 2 10 14 120 0 lfm air flow 200 lfm air flow 400 lfm air flow ltm4634 4634f for more information www.linear.com/ltm4634
24 a pplica t ions i n f or m a t ion table 2. 3.3v output derating curve v in (v) power loss curve air flow (lfm) heat sink ja (c/w) figures 15, 19 12, 24 figures 8 to 13 0 none 9.0 figures 15, 19 12, 24 figures 8 to 13 200 none 7.5 figures 15, 19 12, 24 figures 8 to 13 400 none 6.5 figures 14, 18 12, 24 figures 8 to 13 0 bga heat sink 9.0 figures 14, 18 12, 24 figures 8 to 13 200 bga heat sink 6.5 figures 14, 18 12, 24 figures 8 to 13 400 bga heat sink 6.0 table 3. 5v output derating curve v in (v) power loss curve air flow (lfm) heat sink ja (c/w) figures 17, 20 12, 24 figures 8 to 13 0 none 9.0 figures 17, 20 12, 24 figures 8 to 13 200 none 7.5 figures 17, 20 12, 24 figures 8 to 13 400 none 6.5 figures 16, 21 12, 24 figures 8 to 13 0 bga heat sink 9.0 figures 16, 21 12, 24 figures 8 to 13 200 bga heat sink 6.5 figures 16, 21 12, 24 figures 8 to 13 400 bga heat sink 6.0 heat sink manufacturer part number website aavid thermalloy 375424b00034g www.aavid.com cool innovations 4-050503p to 4-050508p www .coolinnovations.com ltm4634 4634f for more information www.linear.com/ltm4634
25 a pplica t ions i n f or m a t ion table 4. output voltage response versus component matrix (refer to figure 26) 0 to 2.5a load step typical measured values c out ceramic vendors value part number murata 220f, 4v, x5r 1206 case size grm31cr60g277m tdk 100f, 6.3v, x5r 1210 case size c3225x5r0j107m murata 22f, 25v, x7r, 1210 case size grm32er71e226k panasonic poscap 100f, 16v, d2 case size 16tqc100m 150f, 16v, d3l case size 16tqc100m murata 4.7f, 50v gru55er71h475k 10f, 50v grm32er71h06ka12l v out1 , v out2 c in (ceramic) c in (bulk)* c out1 (ceramic) c out2 (bulk) c ff c bot c comp v in drop peak-to-peak deviation at 2.5a load step recovery time load step r fb freq 1v 22f 3 150f 100f 2 none 47pf none none 12v 50mv 100mv 90s 2.5a/s 243k 500khz 1v 22f 3 150f 220f 2 none 47pf none none 12v 40mv 80mv 90s 2.5a/s 243k 500khz 1.2v 22f 3 150f 220f 2 none 47pf none none 12v 48mv 96mv 90s 2.5a/s 121k 500khz 1.5v 22f 3 150f 220f 2 none 47pf none none 12v 50mv 100mv 100s 2.5a/s 69.8k 500khz 1.8v 22f 3 150f 220f 2 none 47pf none none 12v 50mv 100mv 100s 2.5a/s 48.7k 500khz 2.5v 22f 3 150f 220f 2 none 47pf none none 12v 75mv 150mv 100s 2.5a/s 28.7k 500khz 2.5v 22f 3 150f 220f 3 none 47pf none none 12v 70mv 140mv 100s 2.5a/s 28.7k 500khz 3.3v 22f 3 150f 220f 2 none 47pf none none 12v 100mv 200mv 120s 2.5a/s 19.1k 500khz 3.3v 22f 3 150f 220f 2 none 47pf none none 12v 100mv 200mv 120s 2.5a/s 19.1k 750khz 3.3v 22f 3 150f 220f 3 none 47pf none none 12v 90mv 180mv 120s 2.5a/s 19.1k 500khz 3.3v 22f 3 150f 100f 2 none 47pf none none 12v 100mv 200mv 120s 2.5a/s 19.1k 750khz 5v 22f 3 150f 100f 2 none 47pf none none 12v 170mv 340mv 100s 2.5a/s 11.5k 750khz 5v 22f 3 150f 100f 3 none 47pf none none 12v 140mv 280mv 100s 2.5a/s 11.5k 750khz v out3 c in ** (ceramic) c in (bulk)* c out1 (ceramic) c out2 (bulk) c ff c bot c comp v in drop peak-to-peak deviation at 2.5a load step recovery time load step r fb freq 5 4.7f 3 150f 100f 2 none 47pf none none 24v 170mv 340mv 120s 2.5a/s 11.5k 600khz 5 4.7f 3 150f 100f 3 none 47pf none none 24v 140mv 280mv 120s 2.5a/s 11.5k 600khz 5 4.7f 3 150f 100f 1 100f 1 47pf none none 24v 120mv 240mv 120s 2.5a/s 11.5k 600khz 5 4.7f 3 150f 22f 1 100f 1 47pf none none 24v 120mv 240mv 120s 2.5a/s 11.5k 600khz 5 4.7f 3 150f 22f 2 100f 1 47pf none none 24v 120mv 240mv 120s 2.5a/s 11.5k 600khz 5 4.7f 3 150f 22f 1 100f 1 47pf none none 24v 110mv 220mv 120s 2.5a/s 11.5k 600khz 5 4.7f 3 150f 22f 2 100f 1 47pf none none 24v 110mv 220mv 120s 2.5a/s 11.5k 600khz 12 4.7f 3 150f 22f 2 none 47pf none none 24v 300mv 600mv 200s 2.5a/s 4.32k 600khz 12 4.7f 3 150f 22f 3 none 47pf none none 24v 300mv 600mv 200s 2.5a/s 4.32k 600khz 12 4.7f 3 150f 22f 1 100f 1 47pf none none 24v 250mv 500mv 200s 2.5a/s 4.32k 600khz 12 4.7f 3 150f 22f 2 100f 1 47pf none none 24v 240mv 480mv 200s 2.5a/s 4.32k 600khz 12 4.7f 3 150f 22f 1 100f 1 47pf none none 24v 230mv 460mv 200s 2.5a/s 4.32k 600khz 12 4.7f 3 150f 22f 2 100f 1 47pf none none 24v 220mv 440mv 200s 2.5a/s 4.32k 600khz *bulk capacitor is optional if vin has very low input impedance. slew rate: 2.5a/s. **50v ltm4634 4634f for more information www.linear.com/ltm4634
26 typical a pplica t ions figure 22. ltm4634 typical 24v input to 3.3v at 5a, 5v at 5a, 12v at 4a r fb3 4.32k r fb2 11.5k r fb1 19.1k c out3 100f 6.3v c out8 22f 16v c out2 100f 6.3v 12v 47pf v fb3 47pf v fb2 47pf v fb1 5v c out5 22f 6.3v c out4 100f 6.3v c out7 22f 16v c out9 22f 16v for c out , r fb , comp and c ff see table 4 c ss3 0.1f c ss1 0.1f 50k c in3 4.7f 50v c in2 4.7f 50v c in1 4.7f 50v c in4 4.7f 50v 100f 50v 10k 10k cntl_pwr mode/pllin run1 run2 run3 tk/ss2 tk/ss3 freq/plllpf comp1 comp2 comp3 pgood12 pgood3 temp1 temp2 v out1 v fb1 v fb1 v out2 v fb2 v out3 v fb3 4634 f22 gnd sgnd v in1 sw1 v in2 24v input sw2 v in3 ltm4634 sw3 4.7f 6.3v intv cc extv cc 5v c ss2 0.1f tk/ss1 1f 2 + 3.3v v fb2 v fb3 ltm4634 4634f for more information www.linear.com/ltm4634
27 typical a pplica t ions figure 23. ltm4634 triple input and triple output (2.5v, 1.5v and 3.3v) at 5a, 5a and 4a r fb3 19.1k v fb3 v fb2 v fb1 r fb2 69.8k r fb1 28.7k c out2 220f 4v c out5 220f 4v c out8 100f 6.3v 3.3v 1.5v 2.5v 47pf v fb1 47pf v fb2 47pf v fb3 c out1 220f 4v c out4 220f 4v c out7 100f 6.3v c ss3 0.1f c ss1 0.1f 120k 50k c in9 22f 6.3v c in8 22f 6.3v 10k 10k cntl_pwr mode/pllin run1 run2 run3 tk/ss2 tk/ss3 freq/plllpf comp1 comp2 comp3 pgood12 pgood3 temp1 temp2 v out1 v fb1 v out2 v fb2 v out3 v fb3 4634 f23 gnd sgnd v in1 sw1 v in2 5v 12v sw2 v in3 ltm4634 sw3 4.7f 6.3v intv cc extv cc c ss2 0.1f tk/ss1 c in6 22f 16v c in5 22f 16v 24v 56f 50v c in2 4.7f 50v c in1 4.7f 50v 5v input 12v input + ltm4634 4634f for more information www.linear.com/ltm4634
28 typical a pplica t ions figure 24. 24v to 12v at 2.8a, then 12v to 1v at 10a r fb3 4.32k r fb1 121k c out3 100f 6.3v c out6 100f 6.3v 12v at 2.8a for other circuits c out2 100f 6.3v 47pf 1v v fb3 47pf 12v out 1v at 10a c out5 100f 6.3v c out1 100f 6.3v c out , see table 4 r fb1 = (60.4k/2)/(v out /0.8) ? 1 c ss3 0.1f 24v 24v 1f 10k 2 120k c ss1 0.22f c in3 22f 16v c in4 22f 16v c out4 100f 6.3v c out7 22f 16v c out8 22f 16v 10k 10k cntl_pwr mode/pllin run2 run3 tk/ss2 tk/ss3 freq/plllpf comp1 comp2 comp3 pgood12 pgood3 temp1 temp2 v out1 v fb1 v fb1 v fb1 v fb3 v out2 v fb2 v out3 v fb3 4634 f24 gnd sgnd v in1 sw1 v in2 12v out at 1.2a sw2 v in3 ltm4634 sw3 4.7f 5v bias intv cc extv cc tk/ss1 24v input c in7 4.7f 50v 56f 50v c in6 4.7f 50v run1 + ltm4634 4634f for more information www.linear.com/ltm4634
29 typical a pplica t ions figure 25. 7v to 28v input, 1.5v, 1.8v and 3.3v at 5a,5a, 4a with tracking r fb3 19.1k r t v in r fb2 48.7k r fb1 69.8k c out4 100f 6.3v 1.5v 1.8v 3.3v c out6 100f 6.3v c out1 100f 6.3v c out2 100f 6.3v c out3 100f 6.3v c out7 100f 6.3v to adc 4634 f25 reduced tracking feedback divider by a factor of 10 to reduce tk/ss current error c ss3 0.22f 4.87k 6.98k 6.04k 3.3v 3.3v 13.3k 1f 2 6.04k c in1 4.7f 50v c in3 4.7f 50v 56f 50v c in2 4.7f 50v 10k 10k 10k 35.7k (400khz) cntl_pwr mode/pllin run1 run2 run3 tk/ss2 tk/ss3 freq/plllpf comp1 comp2 comp3 pgood12 pgood3 temp1 temp2 v out1 v fb1 v out2 v fb2 v out3 v fb3 gnd sgnd v in1 sw1 v in2 7v to 28v input sw2 v in3 ltm4634 sw3 4.7f 6.3v intv cc extv cc 5v bias tk/ss1 + r t v in to adc r t = v in 100a ltm4634 4634f for more information www.linear.com/ltm4634
30 ltm4634 component bga pinout p ackage descrip t ion pin id function pin id function pin id function pin id function pin id function pin id function a1 v out3 b1 v out3 c1 v out3 d1 gnd e1 gnd f1 v in3 a2 v out3 b2 v out3 c2 v out3 d2 gnd e2 gnd f2 v in3 a3 v out3 b3 v out3 c3 v out3 d3 gnd e3 gnd f3 sw3 a4 gnd b4 v out3 c4 v out3 d4 gnd e4 gnd f4 gnd a5 v out2 b5 v out2 c5 temp2 d5 gnd e5 gnd f5 v in2 a6 v out2 b6 v out2 c6 v out2 d6 gnd e6 gnd f6 v in2 a7 v out2 b7 v out2 c7 v out2 d7 gnd e7 gnd f7 sw2 a8 gnd b8 v out2 c8 v out2 d8 gnd e8 gnd f8 gnd a9 gnd b9 v out1 c9 temp1 d9 gnd e9 gnd f9 v in1 a10 v out1 b10 v out1 c10 v out1 d10 gnd e10 gnd f10 v in1 a11 v out1 b11 v out1 c11 v out1 d11 gnd e11 gnd f11 sw1 a12 v out1 b12 v out1 c12 v out1 d12 gnd e12 gnd f12 gnd pin id function pin id function pin id function pin id function pin id function pin id function g1 v in3 h1 v in3 j1 gnd k1 gnd l1 gnd m1 gnd g2 v in3 h2 v in3 j2 gnd k2 gnd l2 gnd m2 pgood12 g3 gnd h3 gnd j3 gnd k3 gnd l3 extv cc m3 pgood3 g4 gnd h4 gnd j4 gnd k4 comp3 l4 comp2 m4 comp1 g5 v in2 h5 v in2 j5 gnd k5 v fb3 l5 v fb2 m5 v fb1 g6 v in2 h6 v in2 j6 cntl_pwr k6 sgnd l6 sgnd m6 gnd g7 gnd h7 gnd j7 gnd k7 sgnd l7 sgnd m7 gnd g8 gnd h8 gnd j8 intv cc k8 gnd l8 freq/plllpf m8 gnd g9 v in1 h9 v in1 j9 gnd k9 gnd l9 mode/pllin m9 tk/ss1 g10 v in1 h10 v in1 j10 gnd k10 gnd l10 run1 m10 tk/ss2 g11 gnd h11 gnd j11 gnd k11 run3 l11 run2 m11 tk/ss3 g12 gnd h12 gnd j12 gnd k12 gnd l12 gnd m12 gnd p ackage p ho t o ltm4634 4634f for more information www.linear.com/ltm4634
31 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. package top view 4 pin ?a1? corner x y aaa z aaa z suggested pcb layout top view bga 144 0613 rev ? ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? 0.0000 0.0000 d a detail b package side view z 0.630 0.025 ? 144x e a2 bga package 144-lead (15mm 15mm 5.01mm) (reference ltc dwg # 05-08-1908 rev ?) 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 detail b substrate a1 b1 ccc z mold cap symbol a a1 a2 b b1 d e e f g h1 h2 aaa bbb ccc ddd eee min 4.81 0.50 4.31 0.60 0.60 0.36 3.95 nom 5.01 0.60 4.41 0.75 0.63 15.00 15.00 1.27 13.97 13.97 0.41 4.00 max 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15 notes dimensions total number of balls: 144 // bbb z z h2 h1 0.0 package bottom view pin 1 detail a ?b (144 places) m x yzddd m zeee e f notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 5. primary datum -z- is seating plane 6. solder ball composition is 96.5% sn/3.0% ag/0.5% cu 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature detail a 3 see notes l k j h g f e d c b m a 12345678 10 9 1112 e g 7 package row and column labeling may vary among module products. review each package layout carefully ! 7 see notes b b ltm4634 4634f for more information www.linear.com/ltm4634
32 ? linear technology corporation 2014 lt 0814 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltm4634 typical a pplica t ion r ela t e d p ar t s r fb3 11.5k r fb1 60.4k 5v at 1a for other circuits c out2 220f 4v 1.2v 5v out c out5 220f 4v c out1 220f 4v c out see table 4 c ss3 0.1f 24v 24v 1f 2 120k c ss1 0.1f c in3 22f 6.3v c in4 22f 6.3v c out4 220f 4v c out7 100f 6.3v c out8 22f 6.3v 10k10k 10k 30k run3 cntl_pwr mode/pllin run2 run3 tk/ss2 tk/ss3 freq/plllpf comp1 comp2 comp3 pgood12 pgood3 temp1 temp2 v out1 v fb1 v fb1 v fb1 47pf v fb3 47pf v out2 v fb2 v out3 v fb3 v fb3 4634 f26 gnd sgnd v in1 sw1 v in2 5v out at 3a sw2 v in3 ltm4634 sw3 4.7f intv cc extv cc 5v out tk/ss1 24v input c in7 4.7f 50v 56f 50v c in6 4.7f 50v run1 + + figure 26. 24v to 5v at 1a, then 5v output to 1.2v at 10a part number description comments ltm4633 triple 10a, 16v in step-down dc/dc module regulator 4.7v v in 16v, 0.8v v out1,2 1.8v, 0.8v v out3 5.5v, pll input, v out soft-start and tracking, pgood, internal temperature monitor, 15mm 15mm 5.01mm bga ltm4630 dual 15v in , 18a or single 36a step-down module regulator with v out up to 1.8v 4.5v v in 15v, 0.6v v out 1.8v, pll input, remote sense amplifier, v out tracking, pgood, clkout, internal temperature monitor, 16mm 16mm 4.41mm lga ltm4644 quad 4a, 14v step-down module regulator with configurable output array 4v v in 14v, 0.6v v out 5.5v, clk input and output, v out tracking, pgood, 9mm 15mm 5.01mm bga l tm4676 dual 13a or single 26a module regulator with digital power system management 4.5v v in 26v, 0.5v v out0 4.0v, 0.5v v out1 5.4v, digital i/f for control and monitoring, integrated 16-bit adc, pmbus compliant i 2 c interface, remote sense amplifiers, 16mm 16mm 5.01mm bga ltm8028 36v in , ultrafast?, low output noise 5a module regulator 6v v in 36v, 0.8v v out 1.8v set via 3-pin three-state interface, <1mv v out ripple, 10% accurate current limit, pgood, 15mm 15mm 4.9mm bga ltm4637 20v in , 20a dc/dc module step-down regulator 4.5v v in 20v, 0.6v v out 5.5v, pll input, v out tracking, remote sense amplifier, pgood, 15mm 15mm 4.32mm lga and 15mm 15mm 4.92mm bga ltm8045 inverting or sepic _module dc/dc converter with up to 700ma output current 2.8v v in 18v, 2.5v v out 15v, synchronizable, no derating or logic-level shift for control inputs when inverting, 6.25mm 11.25mm 4.92mm bga ltc2977 8-channel pmbus power system manager 0.25% tue 16-bit adc, voltage/temperature monitoring and supervision ltc2974 4-channel pmbus power system manager 0.25% tue 16-bit adc, voltage/current/temperature monitoring and supervision ltm4634 4634f for more information www.linear.com/ltm4634

▲Up To Search▲

Price & Availability of LTM4634-15

	To Download LTM4634-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .